1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and, in particular, to the formation of metal lines in BEOL processing.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, complementary MOS (CMOS) technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
The semiconductor manufacturing process typically includes two major components, namely the Front-End-of-Line (FEOL), which includes the multilayer process of forming semiconductor devices (transistors, etc.) on a semiconductor substrate, and the Back-End-Of-Line (BEOL), which includes the metallization after the semiconductor devices have been formed. Proper electrical connection of the semiconductor devices is accomplished by multilayer metallization. Each metallization layer consists of a grid of metal lines sandwiched between one or more dielectric layers for electrical integrity. In fact, manufacturing processes can involve multiple metallization layers. For instance, in forming a copper-based metallization layer, the so-called inlaid or damascene technique is presently a preferred manufacturing method to create metal lines and via. To this end, a dielectric layer, typically comprised of a low-k dielectric, is deposited and patterned so as to receive trenches and vias in accordance with design requirements.
The formation of IC structures on a wafer is usually facilitated by lithographic processes used to transfer a pattern of a reticle (mask, both terms are used interchangeably herein) to a wafer. Patterns can be formed from a photoresist layer disposed on the wafer by passing light energy through a mask having an arrangement to image the desired pattern onto the photoresist layer. As a result, the pattern is transferred to the photoresist layer. In areas where the photoresist is sufficiently exposed, and after a development cycle, the photoresist material becomes soluble such that it can be removed in order to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal-containing layer, a dielectric layer, a hard mask layer, etc.). Portions of the photoresist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). Thereafter, the remaining portions of the photoresist layer can be removed. As an alternative to the described positive tone resist process, the complementary negative tone resist process can be used.
However, at least starting with the 45 nm node, the minimum feature size on the mask has reached sub-wavelength dimensions. Consequently, the so-called optical proximity effect caused by non-uniformity of energy intensity due to optical diffraction during the exposure process occurs. Therefore, optical proximity correction is used to solve pattern deformation caused by the optical proximity effect. The optical proximity effect, due to variations in focus and exposure of the lithography process, leads to parts of the design layout resulting in hot spots in the form of bridging, necking, line-end shortening, etc. Due to the formation of hot spots, printed circuits may fail certain specifications thereby reducing the production yield.
Optical proximity correction (OPC) has been employed in order to reduce pattern deformation (hot spot formation) caused by the optical proximity effect. OPC is the process of correcting the layout of target patterns to be transferred onto a wafer using knowledge of the optical proximity effect. Generally, current OPC techniques involve running a computer simulation that takes an initial data set having information relating to the desired pattern and manipulates the data set to arrive at a corrected data set in an attempt to compensate for the above-mentioned concerns. A reticle can then be made in accordance with the corrected data set. The formed reticle may include “hammerheads” or “serifs” added to line ends to effectively anchor them in place and provide reduced pull back. Moreover, completely independent and non-resolvable assist features may be added to the mask that are intended to modify the aerial image of a nearby main feature to enhance the printability and process tolerance of that main feature. Such features may be provided in the form of scattering bars.
However, due to the ongoing reduction of critical dimensions and semiconductor device features, metal line formation, in particular, on the basis of copper materials in advanced semiconductor manufacturing, in particular, complementary metal-oxide-semiconductor (CMOS) manufacturing, is a critical issue in dense pattern regions. Despite the recent advances in OPC technology, it is still very difficult to form dense metal line structures with very small interspaces between individual metal lines without causing random defects of the formed integrated circuit. Particularly, the formation of copper metal lines poses problems due to the limited ability to fill copper into critical minimum features (trenches, for example). Moreover, densely packed metal lines undesirably show increased resistances and capacitive couplings. In addition, high series resistance of the metal lines, due to design restriction in view of the line width, may result in high current densities, which may lead to degraded performance and reduced reliability due to increased electromigration, i.e., a current induced material flow caused by high current densities.